The present disclosure relates generally to integrated circuits, such as field programmable gate arrays (FPGAs). More particularly, the present disclosure relates to initializing registers (e.g., latches) of an integrated circuit (e.g., an FPGA) using multi-pass configuration.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it may be understood that these statements are to be read in this light, and not as admissions of prior art.
High-performance integrated circuits, such as FPGAs, may contain a large number of bypassable registers (e.g. latches). A user may implement a heavily pipe-lined circuit design on the integrated circuit and achieve high performance. The design may call for some or all of the registers in the integrated circuit to initialize in a specific state. This may be implemented using dedicated initialization hardware built into pipe-lined storage elements, such as using an address line to access transistors to write initialization data. However, dedicated initialization hardware costs silicon area. Additionally, there may be contention between the transistors and components of the registers (e.g., feedback inverters in each latch). Furthermore, testing of the dedicated initialization hardware may incur additional costs. It would be advantageous to initialize the registers without adding dedicated programming hardware to each latch.